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[AK4682] ms0610-e-01 2007/07 - 1 - general description the AK4682 is a single chip codec that includes two channels of adc and four channels of dac. the adc outputs 24bit data and the dac accepts up to 24bit input data. the adc has the enhanced dual bit architecture with wide dynamic range. the dac introduces the new developed advanced multi-bit architecture, and achieves wider dynamic range and lower outband noise. the AK4682 integrates stereo selector supporting 2vrms i/o. the AK4682 has a dynamic range of 96db for adc, 102db for dac and is well suited for digital tv and home theater system. features ? adc/dac part ? asynchronous adc/dac operation ? 8:1 stereo selector for adc input ? 8:3 stereo selector with 2vrms output buffer ? 2-channel 24bit adc - 64x oversampling - sampling rate up to 48khz - linear phase digital anti-alias filter - single-ended input - s/(n+d): 88db - dynamic range, s/n: 96db - digital hpf for offset cancellation - channel independent digital volume (+24/-103db, 0.5db/step) - soft mute ? 4-channel 24bit dac - 128x oversampling - sampling rate up to 192khz - 24bit 8 times digital filter - s/(n+d): 86db - dynamic range, s/n: 102db - channel independent digital volume (+12/-115db, 0.5db/step) - soft mute - de-emphasis filter - output mode: stereo, mono, reverse, mute ? high jitter tolerance ? ttl level digital i/f ? external master clock input: 256fs, 384fs, 512fs 768fs (fs=32khz 48khz) 128fs, 192fs, 256fs 384fs (fs=64khz 96khz) 128fs, 192fs (fs=120khz ~ 192khz) ? 2 audio serial i/f (porta, portb) - master/slave mode (for portb) - i/f format porta: left(24 bit)/right (20/24 bit) justified, i 2 s, tdm portb: left justified, i 2 s ? i 2 c bus p i/f for mode setting ? operating voltage: - digital i/o: 2.7v 5.25v, - analog: 4.75v ~ 5.25v and 8.5v ~ 12.6v ? package: 48pin lqfp (0.5mm pitch) multi-channel codec with 2vrms stereo selector AK4682
[AK4682] ms0610-e-01 2007/07 - 2 - 2ch adc lin1 lin2 lin3 lin4 lin5 lin6 lout1 rout1 lout2 rout2 lout3 rout3 mclkb bickb lrckb sdtob msb rin1 rin2 rin3 rin4 rin5 rin6 sda scl mclka bicka lrcka sdtia1 sdtia2 portb porta 2vrms hpf, dvol serial i/f 2ch dac dvol serial i/f 2ch dac dvol control i/f 2vrms l1 r1 l2 r2 stereo matrix stereo matrix AK4682 block diagram
[AK4682] ms0610-e-01 2007/07 - 3 - ordering guide AK4682eq -20 +85 c 48pin lqfp (0.5mm pitch) akd4682 evaluation board pin layout 37 rin5 36 38 lin3 39 lin4 40 rin4 41 nc 42 43 rin3 44 lin5 45 lin6 46 rin6 47 35 34 33 32 31 avdd2 30 rout3 29 28 27 26 mclkb 1 tvdd 2 lrckb 3 bickb 4 sdtob 5 pdn 6 lrck a 7 bick a 8 9 mclk a 10 sdtia1 11 23 22 21 20 19 18 17 16 15 14 13 rout1 dvss2 dvdd2 lout1 msb scl sda AK4682eq top view nc 48 dvss1 12 24 2 5 nc lout2 rout2 pvss lout3 vcom3 vcom36 lin1 avdd1 lin2 nc avss2 avss1 rin1 rin2 dvdd1 sdtia2 pvdd
[AK4682] ms0610-e-01 2007/07 - 4 - pin/function no. pin name i/o function 1 dvss1 - adc digital ground pin, 0v 2 mclkb i adc master clock input pin 3 tvdd - output buffer power supply pin, 2.7v 5.25v 4 lrckb i/o channel clock b pin 5 bickb i/o audio serial data clock b pin 6 sdtob o audio serial data output b pin 7 pdn i power-down mode & reset pin when ?l?, the AK4682 is powered-down, all registers are reset. and then all digital output pins go ?l?. the AK4682 must be reset once upon power-up. 8 lrcka i input channel clock a pin 9 bicka i audio serial data clock a pin 10 mclka i dac master clock input pin 11 sdtia1 i audio serial data input a1 pin 12 sdtia2 i audio serial data input a2 pin 13 sda i/o control data pin 14 scl i control data clock pin 15 dvdd2 - dac digital power supply pin, 4.75v 5.25v 16 dvss2 - dac digital ground pin, 0v 17 lout1 o lch analog output pin1 18 rout1 o rch analog output pin1 19 msb i portb master mode select pin. ?l?(connected to the gr ound): master/slave mode. ored with msb bit. ?h?(connected to dvdd 2) : master mode. 20 lout2 o lch analog output pin2 21 rout2 o rch analog output pin2 22 pvdd - output buffer power supply pin, 8.5v ~ 12.6v. 23 pvss - output buffer ground pin, 0v. 24 lout3 o lch analog output pin 3 25 rout3 o rch analog output pin 3 26 avdd2 - dac analog power supply pin, 4.75v 5.25v 27 avss2 - dac analog ground pin, 0v 28 vcom36 - common voltage output pin for output buffer. avdd2 x 0.734(typ). 10 f capacitor should be connected to avss2 externally. 29 vcom3 - dac/adc common voltage output pin. avdd2 x 0.6(typ). 10 f capacitor should be connected to avss2 externally. 30 avss1 - adc analog ground pin, 0v 31 avdd1 - adc analog power supply pin, 4.75v 5.25v 32 lin1 i lch input 1 pin 33 rin1 i rch input 1 pin 34 nc - no connection. no internal bonding. this pin should be connected to the ground. 35 lin2 i lch input 2 pin 36 rin2 i rch input 2 pin 37 lin3 i lch input 3 pin 38 rin3 i rch input 3 pin 39 nc - no connection. no internal bonding. this pin should be connected to the ground. 40 lin4 i lch input 4 pin 41 rin4 i rch input 4 pin 42 nc - no connection. no internal bonding. this pin should be connected to the ground.
[AK4682] ms0610-e-01 2007/07 - 5 - pin/function (continued) no. pin name i/o function 43 lin5 i lch input 5 pin 44 rin5 i rch input 5 pin 45 nc - no connection. no internal bonding. this pin should be connected to the ground. 46 lin6 i lch input 6 pin 47 rin6 i rch input 6 pin 48 dvdd1 - adc digital power supply pin, 4.75v 5.25v note: all digital input pins must not be left floating. note: analog input pins (lin1, rin1, lin2, rin2, lin3, rin3, lin4, rin4, lin5, rin5, lin6, rin6 pin) must use the ac-coupling capacitor for signal input. note: analog output pins (lout1, rout1, lout2, rout2, lout3, rout3 pins) must use the ac-coupling capacitor for signal output. handling of unused pin the unused i/o pins should be processed appropriately as below. classification pin name setting analog lout1-3, rout1-3, lin1-6, rin1-6 these pins should be open. sdtob, lrckb(master), bickb(master) these pins should be open. mclka, lrcka, bicka, sdtia1-2, mclkb, lrckb(slave), bickb(slave), msb these pins should be connected to dvss. digital sda, scl these pins should be pulled-up to dvdd2.
[AK4682] ms0610-e-01 2007/07 - 6 - absolute maximum ratings (avss1, avss2, dvss1, dvss2, pvss=0v; note: 1) parameter symbol min max units power supply tvdd dvdd1 dvdd2 avdd1 avdd2 pvdd -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 6.0 6.0 6.0 6.0 6.0 14.0 v v v v v v input current (any pins except for supplies) iin - 10 ma digital input voltage 1 (mclkb pin) vind1 -0.3 dvdd1+0.3 v digital input voltage 2 (pdn, lrcka, bicka, mclka, sdtia1-2, sda, scl, msb pins) vind2 -0.3 dvdd2+0.3 v digital input voltage 3 (lrckb, bickb pins) vind3 -0.3 tvdd+0.3 v analog input voltage 1 (lin1-6, rin1-6 pins) vina1 -0.3 pvdd+0.3 v ambient operating temperature ta -20 85 c storage temperature tstg -65 150 c note: 1. avss1, dvss1, avss2, dvss2 and pvss must be connected to the same analog ground plane. warning: operation at or beyond these limits may result in permanent damage to the device. normal operation is not guaranteed at these extremes. recommended operating conditions (avss1, avss2, dvss1, dvss2, pvss=0v; note: 1) parameter symbol min typ max units power supply ( note: 2) tvdd dvdd1 dvdd2 avdd1 avdd2 pvdd 2.7 4.75 4.75 4.75 4.75 8.5 3.3 5.0 5.0 5.0 5.0 9.0 5.25 5.25 5.25 5.25 5.25 12.6 v v v v v v note: 2. the avdd1, avdd2, dvdd1 and dvdd2 must be the same voltage. the tvdd must not exceed any of avdd1, avdd 2, dvdd1 and dvdd2 voltage. *akemd assumes no responsibility for the usage beyond the conditions in this datasheet.
[AK4682] ms0610-e-01 2007/07 - 7 - analog characteristics (ta=25 c; tvdd = 3.3v; dvdd1, dvdd2, avdd1, avdd2= 5.0v; pvdd = 9v; avss1, avss2, dvss1, dvss2, pvss = 0v; fs=48khz; bick=64fs; signal frequency=1khz; 24bit data; measurement frequency = 20hz 20khz at fs=48khz, 20hz~40khz at fs=96khz; 20hz~40khz at fs=192khz, all blocks are synchronized, unless otherwise specified) parameter min typ max units analog input to analog output characteristics (lin1-6, rin1-6 pin to lout1-3, rout1-3 pin) s/(n+d) input=2vrms - 92 db s/n input=0ff, a-weighted - 96 db input impedance 40 k maximum input voltage ( note: 4) 2 - - vrms gain - 0 - db analog input (lin1-6, rin1-6 pin) to adc analog input characteristics resolution 24 bits s/(n+d) (-1dbfs) fs=48khz 80 88 db dr (-60dbfs) fs=48khz, a-weighted 88 96 db s/n (input off) fs=48khz, a-weighted 88 96 db interchannel isolation ( note: 3) 90 100 db interchannel gain mismatch 0.2 0.6 db gain drift 50 - ppm/ c input voltage ain= 2.2 x avdd1/5 2 2.2 2.4 vrms power supply rejection ( note: 5) 60 db dac to analog output (lout1-3, rout1-3 pin) characteristics resolution 24 bits s/(n+d) (0dbfs) fs=48khz fs=96khz fs=192khz 76 - - 86 84 84 db db db dr (-60dbfs) fs=48khz, a-weighted fs=96khz fs=96khz, a-weighted fs=192khz fs=192khz, a-weighted 94 - - - - 102 96 102 96 102 db db db db db s/n (?0? data) fs=48khz, a-weighted fs=96khz fs=96khz, a-weighted fs=192khz fs=192khz, a-weighted 94 - - - - 102 96 102 96 102 db db db db db interchannel isolation 90 100 db interchannel gain mismatch 0.2 0.5 db gain drift 50 - ppm/ c output voltage aout= 2 x avdd2/5 1.85 2 2.15 vrms load resistance (ac load) 5 k load capacitance 30 pf power supply rejection ( note: 5) 50 db note: 3. this value is the interchannel isolation between all the channels of the lin1-6 and rin1-6. note: 4. maximum input level that satisfy s/(n+d)>80db. note: 5. psr is applied to avdd1, avdd2, dvdd1, dvdd2 and pvdd with 1khz, 50mvpp.
[AK4682] ms0610-e-01 2007/07 - 8 - power supplies parameter min typ max units power supply current normal operation (pdn pin = ?h?) tvdd dvdd1+avdd1 dvdd2+avdd2 pvdd power-down mode (pdn pin = ?l?; note: 6) tvdd dvdd1+avdd1 dvdd2+avdd2 pvdd 1 37 33 15 10 10 10 10 3 55 50 25 100 100 100 100 ma ma ma ma a a a a note: 6. all digital inputs including clock pins (mclka, mclkb, bicka, bickb, lrcka, lrckb and sdtia1-0) are held at dvdd1, dvdd2, dvss1 or dvss2. filter characteristics (ta=-20 c ~+85 c; tvdd=2.7 ~ 5.25v; dvdd1, dvdd2, avdd1, avdd2=4.75 ~ 5.25v; pvdd=8.5 ~ 12.6v; fs=48khz) parameter symbol min typ max units adc digital filter (decimation lpf): passband ( note: 7) 0.1db -0.2db -3.0db pb 0 - - 20.0 23.0 18.9 - - khz khz khz stopband sb 28.0 khz passband ripple pr 0.04 db stopband attenuation sa 68 db group delay ( note: 8) gd 16 1/fs group delay distortion gd 0 s adc digital filter (hpf): frequency response ( note: 7) -3db -0.1db fr 1.0 6.5 hz hz dac digital filter: passband ( note: 7) -0.1db -6.0db pb 0 - 24.0 21.8 - khz khz stopband sb 26.2 khz passband ripple pr 0.02 db stopband attenuation sa 54 db group delay ( note: 8) gd 20 1/fs dac digital filter + analog filter: frequency response: 0 20.0khz 40.0khz ( note: 9) 80.0khz ( note: 9) fr fr fr 0.2 0.3 1.0 db db db note: 7. the passband and stopband frequencies scale with fs. for example, 21.8khz at ?0.1db is 0.454 x fs (dac). the reference frequency of these responses is 1khz. note: 8. the calculating delay time occurred at digital filteri ng. this time is from setting the input of analog s signal to setting the 24bit data of both channels to the output register of portb. for dac, this time is from setting the 20/24bit data of both channels on input register of porta to the output of analog signal. note: 9. 40.0khz@fs=96khz, 80.0khz@fs=192khz.
[AK4682] ms0610-e-01 2007/07 - 9 - dc characteristics (ta=-20 c ~+85 c; tvdd=2.7 ~ 5.25v; dvdd1, dvdd2, avdd1, avdd2=4.75 ~ 5.25v; pvdd=8.5 12.6v) parameter symbol min typ max units high-level input voltage low-level input voltage vih vil 2.2 - - - - 0.8 v v high-level output voltage ( iout=-400 a) low-level output voltage (iout= -400 a(except sda pin), 3ma(sda pin)) voh vol tvdd-0.4 - - - 0.4 v v input leakage current iin - - 10 a switching characteristics (ta=-20 c ~+85 c; tvdd=2.7 ~ 5.25v; dvdd1, dvdd2, avdd1, avdd2=4.75 ~ 5.25v; pvdd=8.5 12.6v; c l = 20pf (except for sda pin), cb=400pf(sda pin)) parameter symbol min typ max units master clock timing frequency duty feclk declk 8.192 40 50 36.864 60 mhz % master clock ( note: 10) 256fsn, 128fsd: pulse width low pulse width high 384fsn, 192fsd: pulse width low pulse width high 512fsn, 256fsd, 128fsq: pulse width low pulse width high 768fsn, 384fsd, 192fsq: pulse width low pulse width high fclk tclkl tclkh fclk tclkl tclkh fclk tclkl tclkh fclk tclkl tclkh 8.192 27 27 12.288 20 20 16.384 15 15 24.576 10 10 12.288 18.432 24.576 36.864 mhz ns ns mhz ns ns mhz ns ns mhz ns ns lrcka (lrckb) timing (slave mode) normal mode normal speed mode double speed mode quad speed mode duty cycle fsn fsd fsq duty 32 64 120 45 48 96 192 55 khz khz khz % tdm 128 mode lrcka frequency ?h? time ?l? time fs tlrh tlrl 32 1/128fs 1/128fs 96 khz ns ns lrckb timing (master mode) normal mode lrckb frequency duty cycle fs duty 32 50 48 khz % power-down & reset timing pdn pulse width ( note: 11) pdn ? ? to sdtob valid ( note: 12) tpd tpdv 150 522 ns 1/fs note: 10 mclkb supports only the normal mode (256fsn, 384fsn, 512fsn, 768fsn). note: 11 the AK4682 can be reset by bringing the pdn pin = ?l?. note: 12 these cycles are the number of lrckb rising from pdn rising.
[AK4682] ms0610-e-01 2007/07 - 10 - parameter symbol min typ max units audio interface timing (slave mode) normal mode(porta) bicka period bicka pulse width low pulse width high lrcka edge to bicka ? ? ( note: 13) bicka ? ? to lrcka edge ( note: 13) sdtia1-2 hold time sdtia1-2 setup time tbck tbckl tbckh tlrb tblr tsdh tsds 81 32 32 20 20 10 10 ns ns ns ns ns ns ns normal mode(portb) bickb period bickb pulse width low pulse width high lrckb edge to bickb ? ? ( note: 13) bickb ? ? to lrckb edge ( note: 13) lrckb to sdtob (msb) bickb ? ? to sdtob tbck tbckl tbckh tlrb tblr tlrs tbsd 324 128 128 80 80 80 80 ns ns ns ns ns ns ns tdm 128 mode bicka period bicka pulse width low pulse width high lrcka edge to bicka ? ? ( note: 13) bicka ? ? to lrcka edge ( note: 13) sdtia1-2 hold time sdtia1-2 setup time tbck tbckl tbckh tlrb tblr tsdh tsds 81 32 32 20 20 10 10 ns ns ns ns ns ns ns audio interface timi ng (master mode) normal mode bickb frequency bickb duty bickb ? ? to lrckb edge bickb ? ? to sdto fbck dbck tmblr tbsd -40 64fs 50 40 20 hz % ns ns control interface timing (i 2 c bus): scl clock frequency bus free time between transmissions start condition hold time (prior to first clock pulse) clock low time clock high time setup time for repeated start condition sda hold time from scl falling ( note: 14) sda setup time from scl rising rise time of both sda and scl lines fall time of both sda and scl lines setup time for stop condition pulse width of spike noise suppressed by input filter capacitive load on bus fscl tbuf thd:sta tlow thigh tsu:sta thd:dat tsu:dat tr tf tsu:sto tsp cb - 1.3 0.6 1.3 0.6 0.6 0 0.1 - - 0.6 - 0 400 - - - - - - - 0.3 0.3 - 50 400 khz s s s s s s s s s s ns pf note: 13 bick rising edge must not occur at the same time as lrck edge. note: 14 data must be held for sufficient time to bridge the 300 ns transition time of scl. note: 15 i 2 c is a registered trademark of philips semiconductors.
[AK4682] ms0610-e-01 2007/07 - 11 - timing diagram 1/fclk tclkl vih tclkh mclk vil 1/fsn, 1/fsd, 1/fsq lrck vih vil tbck tbckl vih tbckh bick vil clock timing (normal mode) 1/fclk tclkl vih tclkh mclk vil 1/fsn, 1/fsd lrck vih vil tlrl tlrh tbck tbckl vih tbckh bick vil clock timing (tdm 128 mode) lrck= lrckb, lrcka, bick= bicka, bickb, sdti= sdtia, sdto= sdtob.
[AK4682] ms0610-e-01 2007/07 - 12 - tlrb lrck vih bick vil tlrs sdto 50% tvdd tbsd vih vil tblr tsds sdti vih vil tsdh audio interface timing (normal mode) tlrb lrck vih bick vil sdto 50%tvdd tbsd vih vil tblr tsds sdti vih vil tsdh audio interface timing (tdm 128 mode)
[AK4682] ms0610-e-01 2007/07 - 13 - lrck bick sdto tbsd tmblr 50% tvdd 50% tvdd 50% tvdd audio interface timing (master mode) tpd vil pdn tpdv sdto 50% tvdd vih power down & reset timing thigh scl sda vih tlow tbuf thd:sta tr tf thd:dat tsu:dat tsu:sta stop start start stop tsu:sto vil vih vil tsp i 2 c bus mode timing
[AK4682] ms0610-e-01 2007/07 - 14 - operation overview system clock the AK4682 has two audio serial interface (porta, portb) can operate asynchronously. at each port, the external clocks, which are required to operate the AK4682, ar e mclka (mclkb), lrcka (lrckb) and bicka (bickb). the mclka (mclkb) must be synchronized with lrcka (lrck b) but the phase is not critical. the port a is the audio data interface for dac and the portb is for adc. master/slave mode the msb pin and msb bit are internally or ed and select the master/slave mode of portb. porta is slave mode only. in master mode, lrckb pin and bickb pin are output pins. in slave mode, lrcka (lrckb) pin and bicka (bickb) pin are input ( table 1). the AK4682 is slave mode at power-down (pdn pin = ?l?). to change to the master mode, set msb pin ?h? or write ?1? to msb bit. until when setting msb pin ?h? or writing ?1? to msb bit, lrckb and bickb pins are input pins. pull-up (or down) resistor with around 100kohm is re quired to prevent the floating of these input pins. pdn pin msb pin msb bit (default: ?0?) portb (adc) bickb, lrckb porta (dac) bicka, lrcka l x input (slave mode) input (slave mode) l h x output ?l?(master mode) input (slave mode) l 0 input (slave mode) input (slave mode) l 1 output (master mode) input (slave mode) h h x output (master mode) input (slave mode) (x: don?t care) table 1. master/salve mode adc clock control in master mode (msb bit = ?1?), the cksb1-0 bits select the clock frequency ( table 2). the external clock (mclkb) must always be supplied except in the power-down mode. the adc is in power-down mode until mclkb is supplied. cksb1 cksb0 clock speed 0 0 256fs (default) 0 1 384fs 1 0 512fs 1 1 768fs table 2. portb master clock control (adc master mode) in slave mode (msb bit = ?0?. default) , external clocks (mclkb, bickb, lrck b) must always be present whenever the adc is in normal operation mode (pdn pin = ?h? and pwad = ?1?). the master clock (mclkb) must be synchronized with lrckb but the phase is not critical. if these clocks are not provided, the adc may draw excess current because the device utilizes dynamic refreshed logic internally. if the external cloc ks are not present, the adc must be in the power-down mode (pdn pin = ?l? or pwad = ?0?) or in the reset mode (rstn bit = ?0?). after exiting reset at power-up etc., the adc is in the power-down mode until mclkb and lrckb are input.
[AK4682] ms0610-e-01 2007/07 - 15 - lrckb mclkb (mhz) fs 128fs 192fs 256fs 384fs 512fs 768fs sampling speed 32.0khz - - 8.1920 12.2880 16.3840 24.5760 44.1khz - - 11.2896 16.9344 22.5792 33.8688 48.0khz - - 12.2880 18.4320 24.5760 36.8640 normal table 3. system clock example (adc slave mode) dac clock control external clocks (mclka, bicka, lrcka) must always be present whenever the dac is in normal operation mode (pdn pin = ?h? and pwda = ?1?). the master clock (mclka) must be synchronized with lrcka but the phase is not critical. if these clocks are not provided, the dac ma y draw excess current because the device utilizes dynamic refreshed logic internally. if the external clocks are not present, the dac must be in the power-down mode (pdn pin = ?l? or pwda = ?0?) or in the reset mode (rstn bit = ?0?) . after exiting reset at power-up etc., the dac is in the power-down mode until mclka and lrcka are input. there are two modes for controlling the sampling speed of dac. one is the manual setting mode (acks bit = ?0?) using the dfs1-0 bits, and the other is auto setting mode (acks bit = ?1?). 1. manual setting mode (acks bit = ?0?) when the acks bit = ?0?, dac is in manual setting mode and the sampling speed is selected by dfs1-0 bits ( table 4). dfs1 dfs0 dac sampling speed (fs) 0 0 normal speed mode 32khz~48khz 0 1 double speed mode 64khz~96khz (default) 1 0 quad speed mode 120khz~192khz 1 1 not available - (note: adc is always in normal speed mode) table 4.dac sampling speed (acks bit = ?0?, manual setting mode) lrcka mclka (mhz) bicka (mhz) fs 256fs 384fs 512fs 768fs 64fs 32.0khz 8.1920 12.2880 16.3840 24.5760 2.0480 44.1khz 11.2896 16.9344 22.5792 33.8688 2.8224 48.0khz 12.2880 18.4320 24.5760 36.8640 3.0720 table 5. dac system clock example (dac normal speed mode @manual setting mode) lrcka mclka (mhz) bicka (mhz) fs 128fs 192fs 256fs 384fs 64fs 88.2khz 11.2896 16.9344 22.5792 33.8688 5.6448 96.0khz 12.2880 18.4320 24.5760 36.8640 6.1440 table 6. dac system clock example(dac double speed mode @manual setting mode)
[AK4682] ms0610-e-01 2007/07 - 16 - lrcka mclka (mhz) bicka (mhz) fs 128fs 192fs 256fs 384fs 64fs 176.4khz 22.5792 33.8688 - - 11.2896 192.0khz 24.5760 36.8640 - - 12.2880 table 7. dac system clock example (dac quad speed mode @manual setting mode) 2. auto setting mode (acks bit = ?1?) when the acks bit = ?1?, dac is in auto setting mode and the sampling speed is selected automatically by the ratio mclka/lrcka as shown in the table 8. and the internal master clock is set to the appropriate frequency ( table 9). in this mode, the setting of dfs1-0 bits are ignored. mclka dac sampling speed (fs) lrcka 512fs, 768fs normal speed mode 32khz~48khz 256fs, 384fs double speed mode 64khz~96khz 128fs, 192fs quad speed mode 120khz~192khz (note: adc is always in normal speed mode) table 8. dac sampling speed (acks bit = ?1?, auto setting mode) lrcka mclka (mhz) fs 128fs 192fs 256fs 384fs 512fs 768fs sampling speed 32.0khz - - - - 16.3840 24.5760 44.1khz - - - - 22.5792 33.8688 48.0khz - - - - 24.5760 36.8640 normal 88.2khz - - 22.5792 33.8688 - - 96.0khz - - 24.5760 36.8640 - - double 176.4khz 22.5792 33.8688 - - - - 192.0khz 24.5760 36.8640 - - - - quad table 9. dac system clock example (auto setting mode) dac audio data control the dac1, dac2 bits select the output data for each dac. dac1 bit dac1 source normal mode tdma bit = ?0? tdm mode tdma bit = ?1? 0 sdtia1 l1, r1 1 sdtia2 l2, r2 (default) table 10. dac1 source control dac2 bit dac2 source normal mode tdma bit = ?0? tdm mode tdma bit = ?1? 0 sdtia1 l1, r1 1 sdtia2 l2, r2 (default) table 11. dac2 source control
[AK4682] ms0610-e-01 2007/07 - 17 - de-emphasis filter the AK4682 includes the digital de-emphasis filter (tc=50/15 s) by iir filter. this filter corresponds to three sampling frequencies (32khz, 44.1khz, 48khz). de -emphasis filter is off in double sp eed mode and quad speed mode. de- emphasis of each dac can be set individually by register. mode dem11 (dem21) dem10 (dem20) dem 0 0 0 44.1khz 1 0 1 off 2 1 0 48khz 3 1 1 32khz (default) table 12. de-emphasis control adc digital high pass filter the adc has a digital high pass filter for dc offset cancel. the cut-off frequency of the hp f is 1.0hz at fs=48khz and scales with sampling rate (fs). audio serial interface format each porta/b can select independent audio interface format. the tdma, difa1- 0 bits control the audio format for porta and support normal mode and tdm128 mode. the difb1-0 bits control the audio format for portb and support only normal mode. the default is mode 2. in all modes the serial data is msb-first, 2?s complement format. the sdtob pins are clocked out on the falling edge of bickb pins and the sdtia1-0 pins are latched on the rising edge of bicka pins. 1. setting for the porta 1-1. normal mode: tdma bit = ?0? (default) the tdma bit = ?0? sets the AK4682 audio serial interface format to th e normal mode. the difa1-0 bits select following eight serial data format ( table 13). lrcka bicka mode difa1 bit difa0 bit sdtia1-2 l/r i/o speed i/o 0 0 0 20bit, right justified h/l i 48fs i 1 0 1 24bit, right justified h/l i 48fs i 2 1 0 24bit, left justified h/l i 48fs i 3 1 1 24bit, i 2 s l/h i 48fs i (default) table 13 audio interface format (normal mode.) 1-2. tdm 128 mode: tdma bit = ?1? the tdma bits = ?1? set the AK4682 au dio serial interface format to the td m 128 mode. the four channel serial data (sdtia1, 2) is input to the sdtia1 pin. the data of sdtia2 pin is not used. the tdm 128 mode is not available in quad speed mode. lrcka bicka mode difa1 bit difa0 bit sdtia1-2 start i/o speed i/o 8 0 0 20bit, right justified i 128fs i 9 0 1 24bit, right justified i 128fs i 10 1 0 24bit, left justified i 128fs i 11 1 1 24bit, i 2 s i 128fs i (default) table 14. audio interface fo rmat (tdm 128 mode.)
[AK4682] ms0610-e-01 2007/07 - 18 - 2. setting for the portb 2-1: normal mode: the portb supports only the normal mode. the difb1-0 bits select following eight serial data format ( table 15). lrckb bickb mode msb pin msb bit difb1 difb0 sdtob l/r i/o speed i/o 0 0 0 0 0 24bit, l j h/l i 48fs i 1 0 0 0 1 24bit, l j h/l i 48fs i 2 0 0 1 0 24bit, l j h/l i 48fs i 3 0 0 1 1 24bit, i 2 s l/h i 48fs i (default) 4 0 1 0 0 24bit, l j h/l o 64fs o 5 0 1 0 1 24bit, l j h/l o 64fs o 6 0 1 1 0 24bit, l j h/l o 64fs o 7 0 1 1 1 24bit, i 2 s l/h o 64fs o 8 1 x 0 0 24bit, l j h/l o 64fs o 9 1 x 0 1 24bit, l j h/l o 64fs o 10 1 x 1 0 24bit, l j h/l o 64fs o 11 1 x 1 1 24bit, i 2 s l/h o 64fs o table 15. audio interface format (normal mode, x: don?t care. l j: left justified.)
[AK4682] ms0610-e-01 2007/07 - 19 - lrck bick(64fs) sdto(o) 0 1 2 12 13 14 24 25 31 0 1 2 12 13 14 24 25 31 0 23 1 22 0 23 22 12 11 10 0 23 sdti(i) 1 18 0 19 8 7 1 18 0 19 8 7 lch data rch data don?t care don?t care 12 11 10 sdto-23:msb, 0:lsb; sdti-19:msb, 0:lsb figure 1. mode 0, 4 timing lrck bick(64fs) sdto(o) 0 1 2 8 9 10 24 25 31 0 1 2 8 9 10 24 25 31 0 23 1 22 0 23 22 16 15 14 0 23 sdti(i) 1 22 0 23 8 7 1 22 0 23 8 7 23:msb, 0:lsb lch data rch data don?t care don?t care 16 15 14 figure 2. mode 1, 5 timing lrck bick(64fs) sdto(o) 0 1 2 21 22 23 24 31 0 1 2 0 23 1 22 1 23 22 23 sdti(i) 22 23 0 22 23 23:msb, 0:lsb lch data rch data don?t care 2 2 1 28 29 30 23 0 22 23 24 31 1 0 don?t care 2 21 28 29 30 0 figure 3.mode 2, 6 timing lrck bick(64fs) sdto(o) 0 1 2 3 22 23 24 25 0 0 1 sdti(i) 31 29 30 23 22 1 22 23 0 23:msb, 0:lsb lch data rch data don?t care 2 2 1 0 2 3 22 23 24 25 0 31 29 30 23 22 1 22 23 0 don?t care 2 21 0 1 figure 4. mode 3, 7 timing
[AK4682] ms0610-e-01 2007/07 - 20 - 128 bick bicka(128fs) l1 32 bick r1 32 bick l2 32 bick r2 32 bick (don?t care) sdtia1(i) 18 0 18 0 18 0 18 0 19 19 19 19 19 lrcka sdtia2(i) (mode 8) figure 5. mode 8 timing 128 bick bicka(128fs) (mode 9) l1 32 bick r1 32 bick l2 32 bick r2 32 bick sdtia1(i) 22 0 22 0 22 0 22 0 23 23 23 23 19 lrcka (don?t care) sdtia2(i) figure 6. mode 9 timing 128 bick bicka(128fs) l1 32 bick r1 32 bick l2 32 bick r2 32 bick lrcka sdtia1(i) 22 0 22 0 22 0 22 0 23 23 23 23 22 23 (mode 10) (don?t care) sdtia2(i) figure 7. mode 10 timing
[AK4682] ms0610-e-01 2007/07 - 21 - 128 bick bicka(128fs) l1 32 bick r1 32 bick l2 32 bick r2 32 bick sdtia1(i) 22 0 22 0 22 0 22 0 23 23 23 23 23 lrcka (mode 11) (don?t care) sdtia2(i) figure 8. mode 11 timing
[AK4682] ms0610-e-01 2007/07 - 22 - digital volume control the AK4682 has channel-independent digital volume control ( 256 levels, 0.5db step). the iatl7-0, iatr7-0 bits set the volume level of each adc channel ( table 16). the oat1l7-0, oat1r7-0, oat2l7-0 and oat2r7-0 bits set each dac channel ( table 17). iatl7-0, iatr7-0 attenuation level 00h +24db 01h +23.5db 02h +22.0db : : 2fh +0.5db 30h 0db 31h -0.5db : feh -103db ffh mute (- ) (default) table 16.adc digital volume (iatt) oat1l7-0, oat1r7-0, oat2l7-0, oat2r7-0 attenuation level 00h +12db 01h +11.5db 02h +11.0db : : 17h +0.5db 18h 0db 19h -0.5db : feh -115db ffh mute (- ) (default) table 17.dac digital volume (oatt) atsad (atsda) bits ( table 18, table 19) control the transition time of attenuation. the transition between each attenuation level is the soft transitio n. therefore, the switchi ng noise does not occur in the transition. mode atsad att speed 0 0 1061/fs 1 1 256/fs (default) table 18. transition time of attenuation (adc) mode atsda att speed 0 0 1061/fs 1 1 256/fs (default) table 19. transition time of attenuation (dac)
[AK4682] ms0610-e-01 2007/07 - 23 - the transition between set values is soft transition of 1061 levels in mode 0. it takes 1061/fs (22ms@fs=48khz) from 00h to ffh(mute) in mode 0. if pdn pin goes to ?l?, the iatl7-0, iatr7-0 (oat1l7-0, oat1r7-0, oat2l7-0, oat2r7-0) bits are initialized to 30h(18h). the atts goes to their default value when rstn bit = ?0?. when rstn bit return to ?1?, the atts fa de to their current value. soft mute operation the adc and dac have the soft mute function. the soft mu te operation is performed at digital domain. when the smad/smda bits go to ?1?, the output signal is attenuated by - during att_data att transition time ( table 18, table 19) from the current att level. when the smad/smda bits are returned to ?0?, th e mute is cancelled and the output attenuation gradually changes to the att level during att_data att transition time. if the soft mute is cancelled before attenuating to - after starting the operation, the attenuation is discontinued and returned to att level by the same cycle. the soft mute is ef fective for changing the signal source w ithout stopping the signal transmission. smad/smda bits attenuation att level - aout gd gd (1) (2) (3) (1) notes: (1) att_data att transition time ( table 18, table 19). for example, in norm al speed mode, this time is 1061/fs cycles (256/fs) at att_data=00h. att transition of the soft-mute is from 00h to ffh (2) the analog output corresponding to the digital input has a group delay, gd. (3) if the soft mute is cancelled before attenuating to - after starting the operation, the attenuation is discontinued and returned to att level by the same cycle. figure 9. soft mute function
[AK4682] ms0610-e-01 2007/07 - 24 - stereo matrix control the AK4682 has independent stereo matrix control for dac1 and dac2. the pl23-20 and pl13-10 bits control each matrix. pl13 pl12 pl11 pl10 dac1 lch output dac1 rch output note 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 1 mute mute mute mute mute r l (l+r)/2 mute 0 0 0 0 1 1 1 1 0 0 1 1 0 1 0 1 r r r r mute r l (l+r)/2 reverse 1 1 1 1 0 0 0 0 0 0 1 1 0 1 0 1 l l l l mute r l (l+r)/2 stereo (default) 1 1 1 1 1 1 1 1 0 0 1 1 0 1 0 1 (l+r)/2 (l+r)/2 (l+r)/2 (l+r)/2 mute r l (l+r)/2 mono table 20. pl13-10: dac1 stereo matrix control pl23 pl22 pl21 pl20 dac2 lch output dac2 rch output note 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 1 mute mute mute mute mute r l (l+r)/2 mute 0 0 0 0 1 1 1 1 0 0 1 1 0 1 0 1 r r r r mute r l (l+r)/2 reverse 1 1 1 1 0 0 0 0 0 0 1 1 0 1 0 1 l l l l mute r l (l+r)/2 stereo (default) 1 1 1 1 1 1 1 1 0 0 1 1 0 1 0 1 (l+r)/2 (l+r)/2 (l+r)/2 (l+r)/2 mute r l (l+r)/2 mono table 21. pl23-20: dac2 stereo matrix control stereo: normal stereo output reverse: l/r reverse output mono: monaural output mute: mute operation
[AK4682] ms0610-e-01 2007/07 - 25 - the stereo matrix control has the four channel independent soft transition using soft muting function. dac1 lch setting (control register) a ttenuation att level - dac1 lch out gd (1) (2) (1) l (l+r)/2 l (l+r)/2 r l r (1) (3) (3) gd (2) gd (2) l r (1) r notes: (1) att_data att transition time ( table 18, table 19). for example, in norm al speed mode, this time is 1061/fs cycles (256/fs) at att_data=00h. att transition of the soft-mute is from 00h to ffh (2) the analog output corresponding to the digital input has a group delay, gd. (3) if the soft mute is cancelled before attenuating to - after starting the operation, the attenuation is discontinued and returned to att level by the same cycle. figure 10. soft mute function for stereo matrix control
[AK4682] ms0610-e-01 2007/07 - 26 - input selector, input attenuator the AK4682 includes 8:4 stereo input/output selectors. the ain2-0, aout12-10, aout22-20, aout32-30 bits set each input channel ( table 22, table 23, table 24, table 25). to select the dac1 or dac2, set pwad bit = pwda bit = pwana bit = ?1?. ain3 bit ain2 bit ain1 bit ain0 bit input selector 0 0 0 0 lin1 / rin1 (default) 0 0 0 1 lin2 / rin2 0 0 1 0 lin3 / rin3 0 0 1 1 lin4 / rin4 0 1 0 0 lin5 / rin5 0 1 0 1 lin6 / rin6 0 1 1 0 dac1l/dac1r 0 1 1 1 dac2l/dac2r 1 x x x mute table 22. input selector (for adc, x: don?t care) aout13 bit aout12 bit aout11 bit aout10 bit input selector 0 0 0 0 lin1 / rin1 0 0 0 1 lin2 / rin2 0 0 1 0 lin3 / rin3 0 0 1 1 lin4 / rin4 0 1 0 0 lin5 / rin5 0 1 0 1 lin6 / rin6 0 1 1 0 dac1l/dac1r (default) 0 1 1 1 dac2l/dac2r 1 x x x mute table 23. input selector (for l/rout1, x: don?t care) aout23 bit aout22 bit aout21 bit aout20 bit input selector 0 0 0 0 lin1 / rin1 0 0 0 1 lin2 / rin2 0 0 1 0 lin3 / rin3 0 0 1 1 lin4 / rin4 0 1 0 0 lin5 / rin5 0 1 0 1 lin6 / rin6 0 1 1 0 dac1l/dac1r 0 1 1 1 dac2l/dac2r (default) 1 x x x mute table 24. input selector (for l/rout2, x: don?t care) aout33 bit aout32 bit aout31 bit aout30 bit input selector 0 0 0 0 lin1 / rin1 (default) 0 0 0 1 lin2 / rin2 0 0 1 0 lin3 / rin3 0 0 1 1 lin4 / rin4 0 1 0 0 lin5 / rin5 0 1 0 1 lin6 / rin6 0 1 1 0 dac1l/dac1r 0 1 1 1 dac2l/dac2r 1 x x x mute table 25. input selector (for l/rout3, x: don?t care)
[AK4682] ms0610-e-01 2007/07 - 27 - [input selector switching sequence] the input selector should be changed after soft mute to avoid the switching noise of the input selector ( figure 11). 1. enable the soft mute before changing channel. 2. change channel. 3. disable the soft mute. smute a ttenuation channel datt level - (1) (2) lin1/rin1 lin2/rin2 (1) figure 11. input channel sw itching sequence example the period of (1) varies in the setting value of datt. it takes 1028/fs to mute when datt value is +24db. when changing channels, the input channel should be changed during (2). the period of (2) should be around 200ms because there is some dc difference between the channels.
[AK4682] ms0610-e-01 2007/07 - 28 - power on/off sequence the each block of the AK4682 are placed in the power-down mode by bringing pdn pin ?l? and both digital filters are reset at the same time. pdn pin ?l? also reset the control re gisters to their default values. in the power-down mode, the dac outputs go to avdd2 voltage and sdtob pin goes to ?l?. this reset must always be done after power-up. in slave mode, after exiting reset at power-up etc., the da c (adc) starts to operate from the rising edge of lrcka (lrckb) after mlcka (mclkb ), and then the device is in the po wer-down mode until mclka (mclkb) and lrcka (lrckb) are input. in slave mode, the dac (adc) st arts to operate by the input of mlcka (mclkb) after exiting reset. the analog initialization cycle of adc starts after exiting the power-down mode. therefore, the output data, sdtob becomes available after 522/fs cycles of lrckb clock. in case of the dac, an analog initialization cycle starts after exiting the power-down mode. the analog outputs are avdd2 voltage during the initialization. figure 12 shows the sequences of the power-down and the power-up. the adc and all dacs can be powered-down individually by pwad and pwda bits. these bits don?t initialize the internal register values. when pwad b it = ?0?, the sdtob pin goes to ?l?. when pwda bit = ?0?, the dac outputs go to avdd2 voltage. since some click noise may occur, the analog output should muted externally if the click noise influences system application. a dc internal state pdn clock in mclk,lrck,sclk a dc in (analog) a dc out (digital) dac internal state dac in (digital) dac out (analog) external mute mute on (8) power power-down don?t care gd ?0?data power-down ?0?data gd (3) (3) (4) (6) (7) 522/fs init cycle normal operation (1) gd normal operation gd (5) (6) 516/fs init cycle (2) mute on ?0?data ?0?data don?t care (6) notes: (1) the analog part of adc is initiali zed after exiting the power-down state. (2) the analog part of dac is initiali zed after exiting the power-down state. (3) digital output corresponding to analog input and analog output corresponding to digital input have the group delay (gd). (4) adc output is ?0? data at the power-down state. (5) click noise occurs at the end of initialization of the an alog part. please mute the digital output externally if the click noise influences system application. (6) click noise occurs at the rising/falling edge of pdn and at 512/fs after the rising edge of pdn. (7) when the external clocks (mclka (mclkb), bicka (bickb), and lrcka (lrckb)) are stopped, the AK4682 must be in the power-down mode. (8) please mute the analog output externally if th e click noise (6) influences system application. figure 12. power-down/up sequence example
[AK4682] ms0610-e-01 2007/07 - 29 - reset function when rstn bit = ?0?, adc and dacs ar e powered-down but the internal register are not initialized. the dac outputs go to avdd2 voltage and sdtob pins go to ?l?. because some click noise occurs, the analog output should muted externally if the click noise influences system application. the figure 13 shows the power-up sequence. a dc internal state rstn bit normal operation digital block power-down normal operation don?t care gd gd clock in mclk,lrck,sclk a dc in (analog) ?0?data a dc out (digital) normal operation normal operation dac internal state ?0?data dac in (digital) dac out (analog) gd gd (2) (2) (3) (4) (6) (6) (7) internal rstn bit digital block power-down 1~2/fs (8) 4~5/fs (8) (5) 516/fs init cycle (1) notes: (1) the analog part of adc is initialized after exiting the reset state. (2) digital output corresponding to analog input and analog output corresponding to digital input have the group delay (gd). (3) adc output is ?0? data at the power-down state. (4) click noise occurs when the internal rstn bit becomes ?1 ?. please mute the digital output externally if the click noise influences system application. (5) when rstn bit = ?0?, the analog outputs go to avdd2 voltage. (6) click noise occurs at 4 5/fs after rstn bit becomes ?0?, and occurs at 1 2/fs after rstn bit becomes ?1?. this noise is output even if ?0? data is input. (7) the external clocks ( mclka (mclkb), bicka (bickb), lrcka (lrckb)) can be stopped in the reset mode. when exiting the reset mode, ?1? should be written to rstn bit after the external clocks ( mclka (mclkb), bicka (bickb), lrcka (lrckb)) are fed. (8) there is a delay about 4~5/fs from rstn bit ?0? to the internal rstn bit ?0?. figure 13. reset sequence example
[AK4682] ms0610-e-01 2007/07 - 30 - serial control interface AK4682 supports the fast-mode i 2 c-bus system (max: 400khz). 1. data transfer all commands are preceded by a start condition. after th e start condition, a slave address is sent. after the AK4682 recognizes the start c ondition, the device interfaced to the bus waits for the slave address to be transmitted over the sda line. if the transmitted slave address matches an address for one of the devices, the designated slave device pulls the sda line to low (acknowledge). the data transfer is always terminated by a stop condition generated by the master device. 1-1. data validity the data on the sda line must be stable during the high period of the clock. the high or low state of the data line can only change when the clock signal on the scl line is low except for the start and the stop condition. scl sda data line stable : data valid change of data a llowed figure 14. data transfer 1-2. start and stop condition a high to low transition on the sda line while scl is hi gh indicates a start condition. all sequences start from the start condition. a low to high transition on the sda line while scl is high defines a stop condition. all sequences end by the stop condition. scl sda stop condition start condition figure 15. start and stop conditions
[AK4682] ms0610-e-01 2007/07 - 31 - 1-3. acknowledge acknowledge is a software convention used to indicate successful data transfers. the transmitting device will release the sda line (high) after transmitting eight b its. the receiver must pull dow n the sda line during the acknowledge clock pulse so that that it remains stable ?l? during ?h? period of this clock pulse. the AK4682 will generates an acknowledge after each byte has been received. in the read mode, the slave, the AK4682 will transmit eight b its of data, release the sda line and monitor the line for an acknowledge. if an acknowledge is detected and no stop condition is generated by the master, the slave will continue to transmit data. if an acknowledge is not detected, the sl ave will terminate further data transmissions and await the stop condition. scl from master acknowledge data output by transmitter data output by receiver 1 9 8 start condition clock pulse for acknowledge not acknowledge figure 16. acknowledge on the i 2 c-bus 1-4. first byte the first byte, which includes seven bits of slave address an d one bit of r/w bit, is sent after the start condition. if the transmitted slave address matches an address for one of the device, the recei ver who has been addressed pulls down the sda line. the most significant five bits of the slave address are fixed as ?00100?. the next two bits are ?10?. these two bits identify the specific device on the bus. th e eighth bit (lsb) of the first byte (r/w bit) defines whether a write or read condition which the master requests. a ?1? indicates that the r ead operation is to be executed. a ?0? indicates that the write operation is to be executed. 0 0 1 0 0 1 0 r/w figure 17. the first byte
[AK4682] ms0610-e-01 2007/07 - 32 - 2. write operations set r/w bit = ?0? for the write operation of the AK4682. after receipt of the start condition and the first byte, the AK4682 generates an acknowledge, and awaits the second byte (register address). the second byte consists of the address for control registers of AK4682. the format is msb first, and those most significant 3-bits are ?don?t care?. * * * a4 a3 a2 a1 a0 (*: don?t care) figure 18. the second byte after receipt of the second byte, the AK4682 generates an ac knowledge, and awaits the third byte. those data after the second byte contain control data. the format is msb first, 8bits. d7 d6 d5 d4 d3 d2 d1 d0 figure 19. byte structure after the second byte the AK4682 is capable of more than one byte write operation by one sequence. after receipt of the third byte, the AK4682 generates an ack nowledge, and awaits the next data again. the master can transmit more than one words instead of terminating the write cycle after the first data word is transferred. after the receipt of each data, the internal 5bits address counter is incremented by one, and the next data is taken into next address automatically. if the address exceeds 0dh prior to generating the stop condition, th e address counter will ?roll over? to 00h and the previous data will be overwritten. sda s t a r t a c k a c k s slave a ddress a c k register a ddress(n) data(n) p s t o p data(n+x) a c k data(n+1) figure 20. write operation
[AK4682] ms0610-e-01 2007/07 - 33 - 3. read operations set r/w bit = ?1? for the read operation of the AK4682. after transmission of a data, the master can read next address?s data by generating the acknowledge instead of terminating the write cycle after the recei pt of the first data word. after the r eceipt of each data, the internal 5bits address counter is incremented by one, and the next data is taken into next address automatically. if the address exceeds 0dh prior to generating the stop condition, the address coun ter will ?roll over? to 00h and the previous data will be overwritten. the AK4682 supports two basic read operations: current address read and random read. 3-1. current address read the AK4682 contains an internal address counter that maintains the address of the last word accessed, incremented by one. therefore, if the last access (either a read or wr ite) was to address ?n?, the next current read operation would access data from the address ?n+1?. after receipt of the slave addr ess with r/w bit set to ?1?, the AK4682 gene rates an acknowledge, transmits 1byte data which address is set by the internal address counter and increm ents the internal address counte r by 1. if the master does not generate an acknowledge to the data but generate the stop condition, the AK4682 discontinues transmission sda s t a r t a c k a c k s slave a ddress a c k data(n) data(n+1) p s t o p data(n+x) a c k data(n+2) figure 21. current address read 3-2. random read random read operation allows the master to access any memory location at random. prior to issuing the slave address with the r/w bit set to ?1?, the master must first perform a ?dummy? write operation. the master issues the start condition, sl ave address(r/w=?0?) and then the regist er address to read. after the register address?s acknowledge, the master immediately reissues the st art condition and the slave address with the r/w bit set to ?1?. then the AK4682 generates an ackno wledge, 1byte data and increments the internal address counter by 1. if the master does not generate an acknowledge to the data but generate the stop condition, the AK4682 discontinues transmission. sda s t a r t a c k a c k s s s t a r t slave a ddress word a ddress(n) slave a ddress a c k data(n) a c k p s t o p data(n+x) a c k data(n+1) figure 22. random read
[AK4682] ms0610-e-01 2007/07 - 34 - register map addr register name d7 d6 d5 d4 d3 d2 d1 d0 00h powerdown 1 0 0 pwana 0 0 smad smda rstn 01h powerdown 2 0 0 pwda pwad 0 0 0 0 02h audio data format 0 0 difb1 difb0 0 tdma difa1 difa0 03h de-emphasis/ att speed dem21 de m20 dem11 dem10 dac2 dac1 atsad atsda 04h clock control 0 acks dfs1 dfs0 0 cksb1 cksb0 msb 05h stereo matrix control pl23 pl22 pl21 pl20 pl13 pl12 pl11 pl10 06h input selector control 1 aout13 aout12 aout11 aout10 ain3 ain2 ain1 ain0 07h input selector control 2 aout33 aout32 aout31 aout30 aout23 aout22 aout21 aout20 08h adc lch volume iatl7 iatl6 iatl5 iatl4 iatl3 iatl2 iatl1 iatl0 09h adc rch volume iatr7 iatr6 iatr5 iatr4 iatr3 iatr2 iatr1 iatr0 0ah dac1 lch volume oat1l7 oat1l6 oat1l5 oat1l4 oat1l3 oat1l2 oat1l1 oat1l0 0bh dac1 rch volume oat1r7 oat1r6 oat1r5 oat1r4 oat1r3 oat1r2 oat1r1 oat1r0 0ch dac2 lch volume oat2l7 oat2l6 oat2l5 oat2l4 oat2l3 oat2l2 oat2l1 oat2l0 0dh dac2 rch volume oat2r7 oat2r6 oat2r5 oat2r4 oat2r3 oat2r2 oat2r1 oat2r0 note: for addresses from 0eh to 1fh, data must not be written. when pdn pin goes to ?l?, the registers are initialized to their default values. when rstn bit goes to ?0?, the internal timing is reset, but registers are not initialized to their default values. unused bits must contain a ?0? data.
[AK4682] ms0610-e-01 2007/07 - 35 - register definitions addr register name d7 d6 d5 d4 d3 d2 d1 d0 00h powerdown 1 0 0 pwana 0 0 smad smda rstn default 0 0 1 0 0 0 0 1 rstn: internal timing reset 0: reset. registers are not initialized. 1: normal operation (default) smda: dac soft mute enable 0: normal operation (default) 1: all dac outputs soft-muted smad: adc soft mute enable 0: normal operation (default) 1: adc outputs soft-muted pwana: power management for 2vrms analog i/o 0: power off 1: power on (default) addr register name d7 d6 d5 d4 d3 d2 d1 d0 01h powerdown 2 0 0 pwda pwad 0 0 0 0 default 0 0 1 1 0 0 0 0 pwad: power-down control of adc 0: power-down 1: normal operation (default) pwda: full-power-down control of dac1-2 0: power-down 1: normal operation (default) addr register name d7 d6 d5 d4 d3 d2 d1 d0 02h audio data format 0 0 difb1 difb0 0 tdma difa1 difa0 default 0 0 1 1 0 0 1 1 difa1-0, tdma: audio format control for porta refer table 13, table 14. difb1-0: audio format control for portb refer table 15.
[AK4682] ms0610-e-01 2007/07 - 36 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 03h de-emphasis/ att speed dem21 dem20 dem11 dem10 dac2 dac1 atsad atsda default 0 1 0 1 1 0 0 0 atsda: dac digital attenuator transition time control atsad: adc digital attenuator transition time control refer table 18, table 19. dac2-1: dac data control refer table 10, table 11 dem11-10: dac1 de-emphasis filter control dem21-20: dac2 de-emphasis filter control refer table 12. addr register name d7 d6 d5 d4 d3 d2 d1 d0 04h clock control 0 acks dfs1 dfs0 0 cksb1 cksb0 msb default 0 0 0 0 0 0 0 0 msb: adc master/slave control refer table 1. cksb1-0: adc clock control for master mode. refer table 2. dfs1-0: dac sampling speed control these settings are ignored in auto setting mode. refer table 4. acks: dac auto setting mode 0: disable, manual setting mode (default) 1: enable, auto setting mode master clock frequency is detected automatically at acks bit ?1?. in this case, the dfs1-0 bits are ignored. when this bit is ?0?, dfs1-0 bits set the sampling speed mode. addr register name d7 d6 d5 d4 d3 d2 d1 d0 05h stereo matrix control pl23 pl22 pl21 pl20 pl13 pl12 pl11 pl10 default 1 0 0 1 1 0 0 1 pl13-10: dac1 stereo matrix control. refer table 20. pl23-20: dac2 stereo matrix control. refer table 21.
[AK4682] ms0610-e-01 2007/07 - 37 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 06h input selector control 1 aout13 aout12 aout11 aout10 ain3 ain2 ain1 ain0 default 0 1 1 0 0 0 0 0 ain3-0: adc input selector control 0000: lin1/rin1 (default) 0001: lin2/rin2 0010: lin3/rin3 0011: lin4/rin4 0100: lin5/rin5 0101: lin6/rin6 0110: dac1l/dac1r 0111: dac2l/dac2r 1xxx: mute (x: don?t care) aout13-10: l/rout1 input selector control 0000: lin1/rin1 0001: lin2/rin2 0010: lin3/rin3 0011: lin4/rin4 0100: lin5/rin5 0101: lin6/rin6 0110: dac1l/dac1r (default) 0111: dac2l/dac2r 1xxx: mute (x: don?t care) addr register name d7 d6 d5 d4 d3 d2 d1 d0 07h input selector control 2 aout33 aout32 aout31 aout30 aout23 aout22 aout21 aout20 default 0 0 0 0 0 1 1 1 aout23-20: l/rout2 input selector control 0000: lin1/rin1 0001: lin2/rin2 0010: lin3/rin3 0011: lin4/rin4 0100: lin5/rin5 0101: lin6/rin6 0110: dac1l/dac1r 0111: dac2l/dac2r (default) 1xxx: mute (x: don?t care) aout33-30: l/rout3 input selector control 0000: lin1/rin1 (default) 0001: lin2/rin2 0010: lin3/rin3 0011: lin4/rin4 0100: lin5/rin5 0101: lin6/rin6 0110: dac1l/dac1r 0111: dac2l/dac2r 1xxx: mute (x: don?t care)
[AK4682] ms0610-e-01 2007/07 - 38 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 08h adc lch volume iatl7 iatl6 iatl5 iatl4 iatl3 iatl2 iatl1 iatl0 09h adc rch volume iatr7 iatr6 iatr5 iatr4 iatr3 iatr2 iatr1 iatr0 default 0 0 1 1 0 0 0 0 iatl7-0, iatr7-0: adc volume level control refer table 16. addr register name d7 d6 d5 d4 d3 d2 d1 d0 0ah dac1 lch volume oat1l7 oat1l6 oat1l5 oat1l4 oat1l3 oat1l2 oat1l1 oat1l0 0bh dac1 rch volume oat1r7 oat1r6 oat1r5 oat1r4 oat1r3 oat1r2 oat1r1 oat1r0 0ch dac2 lch volume oat2l7 oat2l6 oat2l5 oat2l4 oat2l3 oat2l2 oat2l1 oat2l0 0dh dac2 rch volume oat2r7 oat2r6 oat2r5 oat2r4 oat2r3 oat2r2 oat2r1 oat2r0 default 0 0 0 1 1 0 0 0 oat1l7-0, oat1r7-0, oat2l7-0, oat2 r7-0: dac volume level control refer table 17.
[AK4682] ms0610-e-01 2007/07 - 39 - system design figure 23 shows the system connection diagram. the evaluation board is available which demonstrates application circuits, the optimum layout, power supply arrangements and measurement results. 5v analog a nalog ground digital ground mi cro controller mute 3.3v to 5v digital + 10u 0.1u + 10u 0.1u + 10u 0.1u 5v digital 5v analog + 10u 0.1u analog in analog out 1 lrcka 4 8 2 dvss1 3 lrckb 4 bickb 5 sdtob 6 7 mclkb 8 pdn 9 mclka 10 sdtia1 11 4 7 4 6 4 5 44 4 3 rin3 42 lin3 41 40 3 9 3 8 scl 13 dvdd2 14 dvss2 15 lout1 16 rout1 17 msb 18 lout2 19 rout2 20 21 pvdd 22 pvss 23 35 34 33 32 31 30 29 28 27 26 25 avss1 vcom36 avss2 vcom3 avdd1 avdd2 rout3 AK4682eq tvdd 12 sda 24 36 37 bicka lin1 rin1 lin2 rin2 rin4 lin4 rin5 lin5 rin6 lin6 nc nc nc dvdd1 sdtia2 lout3 nc + + dsp1 dsp2 + 10u 0.1u 5v digital mute mute mute mute mute analog in + 10u 0.1u 9v to 12v analog figure 23. typical connection diagram (master mode) notes: - dvss1, avss1, dvss2, avss2 and pvss must be connected the same analog ground plane.
[AK4682] ms0610-e-01 2007/07 - 40 - 1. grounding and power supply decoupling the AK4682 requires careful attention to power supply and grounding arrangements. avdd1, avdd2, dvdd1, dvdd2, tvdd and pvdd are usually supplied from analog supply in system. if avdd1, avdd2, dvdd1, dvdd2 and tvdd are supplied separately, the power up sequence is not critical. avss1, dvss1, avss2, dvss2 and pvss of the AK4682 must be connected to analog ground plane. system analog ground and digital ground should be connected together near to wh ere the supplies are brought ont o the printed circuit board. decoupling capacitors should be as near to the AK4682 as possible, with th e small value ceramic capaci tor being the nearest. 2. voltage reference inputs the voltage of avdd1 sets the adc input range, avdd2 sets the dac analog output range. vcom3 and vcom36 are signal grounds of this ch ip. an electrolytic capacitor 10 f parallel with a 0.1 f ceramic capacitor attached between these vcom pins and avss1 pin eliminates the effects of high frequency noise. no load current may be drawn from these vcom pins. all signals, especially clocks, s hould be kept away from the avdd1, avdd2, vcom3 and vcom36 pins in order to avoid unwanted coupling into the AK4682. 3. analog inputs the AK4682 receives the analog in put through the single-ended pre-amp using ex ternal resistors. the input range is 2.2 x avdd1/5 vrms (typ. fs=48khz) at each analog input pins. each input pins are biased internally. the adc output data format is 2?s complement. the internal digital hpf removes the dc offset. the AK4682 samples the analog inputs at 64fs. the digital filter rejects noise above the stop band except for multiples of 64fs. the AK4682 includes an anti-aliasing f ilter (rc filter) to attenuate a noise around 64fs. 4. analog outputs the analog outputs are also single-ended and centered on around the avdd2 voltage. the output signal range scales with the supply voltage and nominally 2 x avdd2/5 vrms at each analog output pi ns. the dac input data format is 2?s complement. the output voltage is a positive full sc ale for 7fffffh(@24bit) and a negative full scale for 800000h(@24bit). the ideal output is avdd 2 voltage for 000000h(@24bit). the internal analog filters remove most of the noise generated by the delta-sigma modulator of dac beyond the audio passband. dc offsets on analog outputs are eliminated by ac coupling since dac outputs have dc offsets a few mv. 5. attention to the pcb wiring attention should be given to avoid coupling with other signals on each analog input/output pins. unused input pins among lin1-6 and rin1-6 pins should be left open.
[AK4682] ms0610-e-01 2007/07 - 41 - package 1 12 48 13 7.0 9.0 0.2 7.0 9.0 0.2 0.22 0.08 48pin lqfp(unit: mm) 0.10 37 24 25 36 0.145 0.05 1.40 0.05 0.13 0.13 1.70max 0 10 0.10 m 0.5 0.2 0.5 package & lead frame material package molding compound: epoxy lead frame material: cu lead frame surface treatment: solder (pb free) plate
[AK4682] ms0610-e-01 2007/07 - 42 - marking AK4682eq xxxxxxx 1 1) pin #1 indication 2) asahi kasei logo 3) marking code: AK4682eq 4) date code: xxxxxxx (7 digits) revision history date (yy/mm/dd) revision reason page contents 07/04/24 00 first edition 07/07/02 01 error correct 12 audio interface timing (normal and tdm128 mode) were changed.
[AK4682] ms0610-e-01 2007/07 - 43 - important notice z these products and their specifications ar e subject to change without notice. when you consider any use or applica tion of these products, please make inqu iries the sales office of asahi kasei emd corporation (akemd) or authorized distributors as to current status of the products. z akemd assumes no liability for infringement of any patent, intellectual property, or other rights in the application or use of any information contained herein. z any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. z akemd products are neither intended nor authorized for use as critical components note1) in any safety, life support, or other hazard related device or system note2) , and akemd assumes no responsibility for such use, except for the use approved with the express written consent by re presentative director of akemd. as used here: note1) a critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. note2) a hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy , or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. z it is the responsibility of the buyer or distributor of ak emd products, who distributes, disposes of, or otherwise places the product with a third party, to notify such third party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold akemd harmless from any and all claims arising from the use of said product in the absence of such notification.

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